1. Field of the Invention
The present invention relates to an A/D converter and more particularly, to an A/D converter comprising a ramp voltage generation circuit generating a ramp voltage changing its value monotonically for a certain period, a voltage comparison circuit comprising an arithmetic unit sampling and holding an analog voltage to be converted and comparing the sampled and held analog voltage to be converted with a reference voltage given by a voltage change value of the ramp voltage generated from the ramp voltage generation circuit or a voltage value proportional to the voltage change value, and changing the output when the reference voltage equals the analog voltage to be converted, a counter counting a digital value corresponding to the reference voltage and outputting it, and a latch circuit latching the digital value outputted from the counter and outputting it when the output of the voltage comparison circuit is changed.
2. Description of the Related Art
Recently, high speed and low power consumption are increasingly demanded in an A/D converter used in a solid-state image sensor. In order to satisfy the above demand, a column-type A/D converter is used in many cases (refer to Japanese Unexamined Patent Publication No. 2000-286706).
FIG. 1 is a block diagram showing a conventional column-type A/D converter. A column-type A/D converter 10 comprises an A/D conversion unit 11, a ramp voltage source 14 (ramp voltage generation circuit) generating a ramp voltage VRAMP, and a counter 15 counting a digital value (n-bit binary signal) corresponding to the voltage change value of the ramp voltage and outputting it. The A/D conversion unit 11 comprises an inverter circuit 12, a switch RS to short-circuit an input node CPI and an output node CPO of the inverter circuit 12, a capacitor CS to sample an analog voltage to be converted, a capacitor CR and a switch S3 to transmit the ramp voltage VRAMP having a value changing monotonically for ascertain period to the input node CPI, a switch SS to sample the analog voltage to be converted, and a latch circuit 13 to latch a counter output corresponding to the analog voltage to be converted as circuit elements. Furthermore, in FIG. 1, a pixel part 16 of a solid-state image sensor and a constant current source Ix connected to a node VIN are also illustrated with the column-type A/D converter 10.
The A/D conversion operation of the column-type A/D converter 10 will be described with reference to an operation timing chart shown in FIG. 2.
At a timing t1, when a switch RX of the pixel part 16 is turned on, a node FD is reset to a voltage VDD, the node VIN is charged to a high potential through a MOS transistor MA. In addition, the switch RS is turned on at the same time, and the input node CPI and the output node CPO of the inverter circuit 12 are short-circuited and the input node CPI is automatically reset to an input determination voltage of the inverter circuit 12 (auto-zero level). Although the switch SS is turned on at the same time, switches S3 and TX are in off state.
At a timing t2, when the switch RX is turned off, a reset voltage appears at the node VIN. At a timing t3, when the switch RS is turned off, a reset voltage is sampled in the capacitor CS.
Then, at a timing t4, when the switch TX is turned on, electric charges that are photo-electrically converted by a photoelectric conversion element (photodiode) PD of the pixel part 16 and accumulated are transferred to the node FD, so that the node VIN is shifted to a voltage level (photoelectric conversion level) corresponding to the photo-electrically converted electric charge amount. At a timing t5 after the voltage level of the node VIN has been stabilized, when the switch TX is turned off and the switch S3 is turned on, a voltage difference between the voltage level of the node VIN at that time (photoelectric conversion level) and an initial voltage of the ramp voltage VRAMP is held in the capacitor CR.
Then, at a timing t6, when the switch SS is turned off, a differential value VSIG between the reset voltage (timing t3) and the photoelectric conversion level (timing 6) of the node VIN is held in the input node CPI as the analog voltage to be converted.
At a timing t7, when the voltage value of the ramp voltage VRAMP starts to increase gradually, the voltage of the input node CPI is also increased so as to be proportional to the voltage increase of the ramp voltage VRAMP. In addition, at the timing t7, the counter 15 starts to count at the same time.
At a timing t8, when the voltage level of the input node CPI exceeds the input determination voltage of the inverter circuit 12, the inverter circuit 12 inverts the output level of the output node CPO. The latch circuit 13 holds the value of the counter output in response to the output change of the output node CPO.
Here, the differential value VSIG corresponds to an incident light amount to the photoelectric conversion element PD, and the value of the latched counter output is equal to an A/D converted value (digital value) of the differential value VSIG. Thus, when the A/D converted value held by the latch circuit 13 is outputted, the column-type A/D converter 10 completes the A/D conversion operation of the analog voltage VSIG to be converted.
FIG. 3 shows input/output characteristics of the inverter circuit 12 that compares the analog voltage VSIG to be converted with an increased voltage value of the ramp voltage VRAMP in the column-type A/D converter 10. The inverter circuit 12 compares the difference voltage between the analog voltage VSIG to be converted and the increased voltage value of the ramp voltage VRAMP as its input voltage with the auto-zero level of the input determination voltage.
The auto-zero level is a voltage level provided by short-circuiting the input and output of the inverter circuit 12, and it is a voltage at an intersection of an input/output characteristic curve A of the inverter and a straight line B provided when an input voltage Vin and an output voltage Vout are equal (Vin=Vout).
When it is assumed that threshold values of a P channel-type MOSFET and an N channel-type MOSFET in the inverter circuit 12 are Vthp and Vthn, respectively and their conductive coefficient are βp and βn, since the current amounts flowing through both MOSFETs of the inverter circuit 12 are equal, the following formula 1 is provided. In addition, in the formula 1, VDD is a power supply voltage supplied to a source terminal of the P channel-type MOSFET, and Vx is an auto-zero level and expressed by a formula 2.βn/2×(Vx−Vthn)2=βp/2×(VDD−Vx−Vthp)2   (1)Vx=Vin=Vout   (2)
When the equation of the formula 1 is solved for Vx, the auto-zero level Vx is expressed by the following formula 3.Vx ={(βn/βp)1/2×Vthn+VDD−Vthp}/(1+(βn/βp)1/2)   (3)
FIG. 4 is a schematic block diagram showing a sensor system 100 comprising the above conventional column-type A/D converter. The sensor system 100 comprises a pixel part 16 (sensor unit) of a solid-stage image sensor having a plurality of photoelectric conversion elements in the shape of a matrix, a plurality of AID conversion units 11 each comprising a voltage comparison circuit 17 and a latch circuit 13 provided with respect to each column of the pixel part 16, a ramp wave generation circuit 14, a counter 15 and a control circuit 18. In addition, the pixel part 16 comprises an effective pixel part 16a and an optical black pixel parts 16b provided at a part of the marginal portions of the pixel part 16 and shielded from light. More specifically, according to the pixel part 16, the optical black pixel part 16b is arranged so as to surround an effective pixel part 16a. 
According to the sensor system 100 shown in FIG. 4, the solid-state image sensor such as a CMOS image sensor photo-electrically converts light (incident light) from an object by the photodiode PD shown in FIG. 1 and outputs an analog signal having a current corresponding to the intensity of the light (incident light amount). Here, a noise component called a dark current caused when a pair of electron/hole is generated by heat is superimposed on the analog signal to be converted that is outputted from the photodiode PD in addition to the current corresponding to the intensity of the incident light. Since the signal component provided by the dark current is a noise component, it has to be removed to prevent quality of an image provided from the sensor system 100 from being lowered. Therefore, according to the sensor system 100 shown in FIG. 4, in order to detect the signal component provided by the dark current, the optical black pixel part 16b which is constituted so as to be shielded from light with aluminum and the like and output only the signal component provided by the dark current is provided at a part of the marginal portions of the pixel part 16. In addition, a pixel shielded from light with aluminum and the like is called an optical black pixel (referred to as “OB pixel” occasionally hereinafter) in general.
FIG. 5 is a schematic view showing each OB pixel signal provided from each OB pixel of the optical black pixel part 16b (referred to as “OB part” occasionally hereinafter) and each effective pixel signal provided from each effective pixel of the effective pixel part 16a. 
As shown in FIG. 5, a voltage value of the OB pixel signal outputted from the OB part differs among all the OB pixels and the voltage value of the OB pixel signal from each OB pixel shows a random value. An average value of voltage levels of the OB pixel signals provided from the OB pixels is referred to as the OB level (average noise voltage) hereinafter. In addition, as shown in FIG. 5, the effective pixel signal provided from each effective pixel of the effective pixel part 16a is provided by adding a signal component provided by the photoelectric conversion, to the signal component provided by the dark current (OB level). Data to be obtained from the sensor system 100 is the signal component provided by the photoelectric conversion. That is, a voltage level (signal component 51) provided by subtracting the OB level from the voltage level of the effective pixel signal provided from the effective pixel part 16a is to be obtained.
Meanwhile, when an incident light amount from an object is small such as when a night view is taken by the sensor system 100, the value of the voltage level of the signal component 51 is very small. Therefore, according to a CMOS image sensor, in order to provide an image having high contrast, multiplying the signal component 51 by gain extends an A/D converted result. According to the column-type A/D converter (FIG. 1) of the sensor system 100 shown in FIG. 4, gain to the input signal (analog voltage to be converted) can be changed by changing inclination of the voltage change of the ramp voltage VRAMP. Here, FIG. 6 shows a relation between a voltage waveform of the node CPI and an operation timing and an output value (A/D converted result) of the latch circuit 13 when the inclination of the voltage change of the ramp voltage VRAMP is set to inclined angles θ1 to θ3 (each of the inclined angles θ1 to θ3 is not defined as a geometric angle but defined as an amount of voltage change per unit time). As shown in FIG. 6, when the inclination of the voltage change of the ramp voltage VRAMP is changed to the inclined angles θ1 to θ3, the timing at which the voltage level of the node CPI exceeds the auto-zero level (threshold voltage of the inverter circuit 12) is changed. The latch circuit 13 latches the digital value outputted from the counter 15 when the output of the inverter circuit 12 is changed. Therefore, when the timing at which the voltage level of the node CPI exceeds the auto-zero level is changed, the digital value of the counter 15 latched by the latch circuit 13 is changed. More specifically, when the inclination of the voltage change of the ramp voltage VRAMP is set to the inclined angle θ1, the inclined angle θ2, and the inclined angle θ3, data D3, D2, and D1 are outputted as A/D converted result, respectively. Thus, the A/D converted result (output value of the latch circuit 13) is changed in accordance with the voltage change of the ramp voltage VRAMP. That is, the gain can be set to the analog voltage to be converted that is inputted to the column-type A/D converter 10 shown in FIG. 1 by changing the inclination of the voltage change of the ramp voltage VRAMP.
Here, in the A/D converter, a FS voltage (full scale voltage) is a voltage that defines a range of an input voltage (analog voltage to be converted) that can be converted to the digital value, and the smaller the value of the FS voltage is, the smaller the range of the input voltage that can be measured (that is, dynamic range) is. According to the A/D converter 10 used in the CMOS image sensor and the like, it is desirable that the dynamic range of the signal component 51 provided by the photoelectric conversion is large in order to improve image quality and the like.
Meanwhile, according to the conventional A/D converter 10 shown in FIG. 1, the full scale voltage is assigned to both signal component provided by photoelectric conversion and noise component provided by the dark current. Here, in FIG. 6, references FS3 to FS1 designate the full scale voltages assigned to the signal component 51 provided by photoelectric conversion and the noise component provided by the dark current shown in FIG. 5. Furthermore, according to the A/D converter 10 shown in FIG. 1, the analog voltage to be converted on which the noise component is superimposed is multiplied by the gain. That is, the noise component is multiplied by the gain and as a result, the OB level is increased. Therefore, when the inclination of the voltage change of the ramp voltage VRAMP is controlled so as to be decreased in order to increase the gain in the A/D converter 10 shown in FIG. 1, the ratio of the full scale voltage assigned to the noise component becomes high. Therefore, as shown in FIG. 6, when the inclination of the voltage change of the ramp voltage VRAMP is degreased to the inclined angle θ3 to θ1 to increase the gain on the input signal of the A/D converter, the FS voltage that can be assigned to the signal component 51 provided by the photoelectric conversion is decreased so as to be proportional to the decreases of the FS3 to FS1 in accordance with the decrease of the inclination θ. That is, the problem is that the range of the input voltage that can be measured by the A/D converter (dynamic range) becomes small in accordance with the increase of the gain.
In addition, when only the signal component 51 provided by the photoelectric conversion can be multiplied by the gain, the full scale voltage of the signal component provided by the photoelectric conversion can be increased and the dynamic range of the signal component 51 can be increased. However, according to the conventional A/D converter shown in FIG. 1, not only the signal component 51 provided by the photoelectric conversion but also the OB level shown in FIG. 5 is multiplied by the gain. Thus, when the input signal (analog voltage to be converted) is multiplied by the gain, the problem is that the ratio of the full scale voltage to the signal component 51 provided by photoelectric conversion is decreased, and the dynamic range of the signal component 51 provided by the photoelectric conversion is decreased.
In order to illustrate the above problem, FIG. 7 shows a timing chart of a column-type A/D converter having 10-bit precision. FIG. 7A shows a relation between a voltage waveform of the node CPI, and an operation timing and an output value (A/D converted result) of the latch circuit 13 when gain is 1, and FIG. 7B shows a relation between a voltage waveform of the node CPI, and an operation timing and an output value (A/D converted result) of the latch circuit 13 when gain is 4. According to the column-type A/D converter shown in FIG. 7, it is assumed that a 10-bit counter is used, and an analog voltage is converted to a digital value of “0 (=20)” to “1023 (=210−1)” LSB. Thus, the dynamic range of the column-type A/D converter shown in FIG. 7 is 1024 levels.
A voltage level Vblack_a of an OB pixel signal from an OB part 16b in FIG. 7A is equal to a voltage level Vblack_b of an OB pixel signal from an OB part 16b in FIG. 7B, and expressed by the following formula 4.Vblack—a=Vblack—b=“100” LSB(dec)  (4)
Here, since the gain is set to 1 in FIG. 7A and the gain is set to 4 in FIG. 7B, a relation between an inclination θ_a of the voltage change of the ramp voltage VRAMP in the case of FIG. 7A and an inclination θ_b of the voltage change of the ramp voltage Vramp in the case of FIG. 7B is expressed by the following formula 5 when it is assumed that each inclination is defined not as a geometric angle but as an amount of voltage change per unit time.θ—b=θ—a/4  (5)
Therefore, an A/D converted result DOUT_a of the voltage level Vblack_a of the OB pixel signal in the case where the gain is set to 1 is provided such that DOUT_a=100 (decimal number) according to FIG. 7A. Similarly, an A/D converted result DOUT_b of the voltage level Vblack_b of the OB pixel signal in the case where the gain is set to 4 is provided such that DOUT_b=400 (decimal number) according to FIG. 7B.
Therefore, the dynamic range of 100 is assigned to the noise component and the rest of 923 (=1023−100) is assigned to the signal component provided by the photoelectric conversion when the gain is set to 1 as shown in FIG. 7A. Similarly, the dynamic range of 400 is assigned to the noise component and the rest of 623 (=1023−400) is assigned to the signal component provided by the photoelectric conversion when the gain is set to 4 as shown in FIG. 7B. That is, when the gain is set to 4, the dynamic range for the signal component provided by the photoelectric conversion is 623 that is less than 923 when the gain is set to 1.
Thus, when gain on an inputted analog voltage to be converted is changed by changing inclination of a voltage waveform of a ramp voltage in a single slope-type A/D converter used in a CMOS image sensor and the like, an A/D converter capable of preventing a dynamic range assigned to a signal component provided by photoelectric conversion from being decreased because an OB level (optical black level) contained in an analog voltage to be converted is multiplied by the gain is demanded.